As a density of a memory cell is increased, the number of memory cells connected to a pair of (or one bit line) is increased. Accordingly, parasitic Resistance and Capacitance (RC) of the bit line may be increased and, therefore, the memory cells connected to each bit line may also be increased, which can reduce the speed of reading/writing the device. Further, when one bit line is selected to read or write information, current is provided to or discharged from the capacitance of the bit line. Accordingly, if the memory cells connected to each bit line are increased in number, the capacitance of the bit line may also increase, which can increase the current consumption of the memory product. In order to prevent/reduce this, even though the memory cells are increased in density, the memory cells may be kept constant. However, it may be difficult to prevent the chip from increasing in size, thereby increasing cost.
The changes in memory process technology shows that if the density is increased, a minimal line width of a circuit may be decreased. However, a line width in a core area of the memory may be reduced less than line width in the memory cell area. As the area of the memory cell is reduced, the layout of circuits in the core area connected to the bit lines (e.g., a column pass unit or a precharge unit) may become more difficult.
FIG. 1 is a view illustrating a conventional bit line layout structure in a semiconductor memory device. Referring to FIG. 1, a plurality of local bit line pairs (BLi-BLBi) each include a local bit line (BLi) and a complementary local bit line (BLBi) connected, in the same direction, to a global bit line pair (GBLi-GBLBi) each including a global bit line (GBLi) and a complementary global bit line (GBLBi). In FIG. 1, four local bit line pairs are connected to one global bit line pair. According to FIG. 1, reference numeral 41 denotes a memory cell area, reference numerals 22 and 20 denote interconnection layer areas, and a reference numeral 30 denotes a core area or a cell peripheral area. A first node (N01) connects the global bit line (GBLi) with the local bit lines (BL0, BL1, BL2 and BL3), and a second node (N02) connects the complementary global bit line (GBLBi) with the complementary local bit lines (BL0B, BL1B, BL2B and BL3B).
As described above, conventional bit line layout structures may not be optimal, and the interconnection layer for signal connections may be increased in kind.